1. Field of the Invention
This invention relates to a semiconductor integrated circuit device with multi-layer wiring structure, specifically to a non-volatile semiconductor memory device with a three-dimensional (3-D) cell array structure.
2. Description of the Related Art
A resistance change memory (i.e., resistive RAM; ReRAM), in which the resistance state of cells is reversibly changed by voltage, current or heat and it serves as data, is noticed for succeeding a conventional NAND type flash memory. The ReRAM is suitable for shrinking the cell size and for constituting a cross-point, cell array, and the cell array may be easily stacked three-dimensionally (for example, refer to JPA-P2009-9657A).
Array wirings such as bit lines and word lines, which constitute multi-layered wirings in a 3-D cell array, are coupled to the underlying semiconductor substrate through vertical via-wirings at a wiring hook-up area disposed on the cell array edge. To equalize the property of the multi-layered array wirings as possible, it is in need of taking into consideration the via-contact structure (for example, refer to JPA-P2009-26867A).
Not only in an ReRAM but also in a NAND-type flash memory with NAND strings stacked vertically, multi-layered word lines are used, and it becomes necessary to hook-up the word lines to the underlying semiconductor substrate through via-contacts. A via-contact structure for hooking-up the multiple array lines stacked on a semiconductor substrate in the vertical direction (in z-direction) to the substrate, in which the array lines are inter-connected if necessary, is, for example, referred to as a “zia-contact” structure (for example, refer to JPA-P2006-512776A (PCT/US2003/041446)).